Overview
| Information | 1.62V TO 3.63V Quad UART WITH 32-Byte FIFO |
|---|---|
| Data Bus Interface | Intel, Motorola |
| # of Channels | 4 |
| Max Data Rate 5V (Mbps) | na |
| Max Data Rate 3.3V (Mbps) | 16 |
| Max Data Rate 2.5V (Mbps) | 12.5 |
| Max Data Rate 1.8V (Mbps) | 8 |
| Tx FIFO (Bytes) | 32 |
| Rx FIFO (Bytes) | 32 |
| Auto Flow Control | ✔ |
| Auto RS-485 Half-Duplex Control | |
| Multidrop (9-bit) Mode | |
| Fractional Baud Rate Generator | ✔ |
| Power Down Mode | ✔ |
| Supply Voltage Range VCC (V) | 1.62 to 3.63 |
| Auto RTS/CTS | ✔ |
| Package | LQFP-64 |
| FIFO Level Counters | |
| Selectable/ Programable Trigger Levels | S |
| IrDA Sup | ✔ |
| 5V Tolerant Inputs | |
| Max UART/GPIO Input Voltage (V) | VCC |
| Max UART/GPIO Output Voltage (V) | VCC |
| Temperature Range (°C) | -40 to 85 |
The XR16M564¹ (M564) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M564 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48 and 68 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16M564IV (64-pin) offers three state interrupt output while the XR16M564DIV provides continuous interrupt output. The XR16M564 is compatible with the industry standard ST16C554 and ST16C654/654D.
NOTE: ¹Covered by U.S. Patent #5,649,122.
- Pin-to-pin compatible with ST16C454, ST16C554, TI's TL16C754B and NXP's SC16C754B
- Intel or Motorola Data Bus Interface select
- Four independent UART channels
- Register Set Compatible to 16C550
- Data rates of up to 16 Mbps
- 32 byte Transmit FIFO
- 32 byte Receive FIFO with error tags
- 4 Selectable TX and RX FIFO Trigger Levels
- Automatic Hardware (RTS/CTS) Flow Control
- Automatic Software (Xon/Xoff) Flow Control
- Programmable Xon/Xoff characters
- Wireless Infrared (IrDA 1.0) Encoder/Decoder
- Full modem interface
- 1.62V to 3.63V supply operation
- Sleep Mode with automatic wake-up
- Crystal oscillator or external clock input
- Pb-Free, RoHS Compliant Versions Offered
- Portable Appliances
- Telecommunication Network Routers
- Ethernet Network Routers
- Cellular Data Devices
- Factory Automation and Process Controls
Documentation & Design Tools
All Types
Data Sheets
Application Notes
Schematics & Design Files
Product Briefs & Brochures
User Guides & Manuals
| Type | Title | Version | Date | File Size |
|---|---|---|---|---|
| Data Sheets | XR16M564/564D 1.62V to 3.63V Quad UART with 32-Byte FIFO | 1.0.0 | May 2008 | 1.1 MB |
| Application Notes | AN-204, UART Sleep Mode | 1.0.0 | June 2010 | 515.8 KB |
| Application Notes | DAN-189, MaxLinear UARTs in GPS Applications | 1.0.0 | April 2008 | 139 KB |
| User Guides & Manuals | XR16M654_ Evaluation Board User's Manual | 1 | April 2009 | 114.9 KB |
| Product Brochures | Interface Brochure | R02 | November 2024 | 3.6 MB |
| Schematics & Design Files | PCI Eval Board Schematic | 1.1.0 | April 2009 | 212.8 KB |
| Schematics & Design Files | ISA Eval Board Schematic | 1.1.0 | September 2007 | 187.4 KB |
Quality & RoHS
Parts & Purchasing
| Part Number | Pkg Code | Min Temp | Max Temp | Status | Suggested Replacement | PDN |
|---|---|---|---|---|---|---|
| XR16M564IJ68-F | PLCC68 | -40 | 85 | OBS | XR16M564IV64-F | |
| XR16M564IJ68TR-F | PLCC68 | -40 | 85 | OBS | XR16M564IV64-F | |
| XR16M564IL48-F | QFN48 7x7 | -40 | 85 | OBS | XR16M654IL48-F | |
| XR16M564IL48TR-F | QFN48 7x7 | -40 | 85 | OBS | XR16M564IL48-F | |
| XR16M564IV64-F | LQFP64 | -40 | 85 | OBS | ||
| XR16M564IV64TR-F | LQFP64 | -40 | 85 | OBS | XR16M564IV64-F | |
| XR16M564IV80-F | LQFP80 12x12 | -40 | 85 | OBS | XR16M554IV80-F | |
| XR16M564IV80TR-F | LQFP80 12x12 | -40 | 85 | OBS | XR16M554IV80-F |
Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
| Pkg Code | Details | Quantities | Dimensions |
|---|---|---|---|
| LQFP64 |
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| LQFP80 12x12 |
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| PLCC68 |
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| QFN48 7x7 |
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Notifications
FAQs & Support
Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
For ordering information and general customer service visit our Contact Us page.
Submit a Technical Support Question As a New Question
LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.
You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.
An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.
For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.
The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.
For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.
The UART will enter the sleep mode if the following conditions have been satisfied for all channels:
-Sleep Mode is enabled
-No interrupts are pending
-TX and RX FIFOs are empty
-RX input pin is idling HIGH (LOW in IR mode)
-Valid values in DLL and DLM registers
-Modem input pins are idle (MSR bits 3-0=0x0)
See AN204, UART Sleep Mode for more information on UART Sleep Mode
The UART will wake-up from sleep mode by any of the following conditions on any channel:
-Sleep mode is disabled
-Interrupt is generated
-Data is written into THR
-There is activity on the RX input pin
-There is activity on the modem input pins
If the sleep mode is still enabled and all wake-up conditions have been cleared, it will return to the sleep mode.
See AN204, UART Sleep Mode for more information on UART Sleep Mode
There will be no activity on the XTAL2 output.
See AN204, UART Sleep Mode for more information on UART Sleep Mode
For any UART that has the wake-up indicator interrupt, an interrupt will be generated when the UART wakes up even if no other interrupts are enabled.
See AN204, UART Sleep Mode for more information on UART Sleep Mode
No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.
No, Auto RTS and Auto CTS will work normally without the interrupts enabled.
No, software flow control characters are not loaded into the RX FIFO.
Since 2-character software flow control requires that 2 consecutive flow control characters match before data transmission is stopped or resumes, there is less of a chance that data transmission is stopped because one data byte matched a control character.
Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.
Most UARTs use RTS#, however the XR16C850 and XR16C864 use the OP1# output as the Auto RS485 control output. In addition to using the RTS# output as the Auto RS485 control output, the XR16L784, XR16L788 and XR16V798 can use the DTR# output as the Auto RS485 control output.
The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.
In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.
It is recommended that the FIFO counters at the Scratchpad Register location be used. When transmitting or receiving data, writing to the LCR register could result in transmit and/or receive data errors.
Due to the dynamic nature of the FIFO counters, it is recommended that the FIFO counter registers be read until consecutive reads return the same value.
All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.
For external clock frequencies above 24MHz at the XTAL1 input, a 2K pull-up may be necessary to improve the rise times if there are data transmission errors.
Yes, you can daisy-chain it like that, but only up to 2 times (3 UARTs total in the daisy-chain). The UARTs should be as close as possible.
No, it just has to meet the minimum high and low pulse widths.
Yes, if you are using a UART with a fractional baud rate generator. This provides a divisor feature with a granularity of 1/16, allowing for any baud rate to be generated by any clock frequency, standard or non-standard. Click on the parametric search button of the product family page and find the Fractional Baud Rate Generator column which tells which products have this feature.
They crystal oscillator circuitry is recommended for fundamental frequency crystals only. The maximum frequency for crystals with fundamental frequencies is typically 24MHz. Above that frequency, crystals operate at higher harmonics, which will not work with the recommended crystal oscillator circuitry.
No. It is only required for transmitting and receiving data.
The -F suffix indicates ROHS / Green compliance:
https://www.exar.com/quality-assurance-and-reliability/lead-free-program
https://www.exar.com/quality-assurance-and-reliability/lead-free-program
Visit the product page for the part you are interested in. The part's status is listed in the Parts & Purchasing section. You can also view Product Lifecycle and Obsolescence Information including PDNs (Product Discontinuation Notifications).
To visit a product page, type the part into the search window on the top of the MaxLinear website.
In this example, we searched for XRA1201. Visit the product page by clicking the part number or visit the orderable parts list by clicking "Orderable Parts".
The Parts & Purchasing section of the product page shows the Status of all orderable part numbers for that product. Click Show obsolete parts, to see all EOL or OBS products.
It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf
Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
